The present invention relates to a nonvolatile semiconductor memory device having therein an error checking and correction (hereinafter referred to as ECC), and more particularly to an error-bit generating circuit for use in the nonvolatile semiconductor memory device.
A nonvolatile semiconductor memory device currently in wide use, has been an electrically erasable programmable read only memory (EEPROM) device of floating gate tunnel oxide (FLOTOX) type. There has also been used an EEPROM device capable of performing a data read-out operation on a single byte. However, due to the possible generation of an error bit in such a data read-out operation, there may occur a decrease in the reliability and yield of the EEPROM. Most of the error-bit generation is caused by a data retention defect due to a defect in the tunnel oxide. As the integration of circuitries in the EEPROM is made of larger scale, a probability of error-bit generation in a single byte becomes higher.
In order to overcome a problem described above, an error correction circuit (i.e., and "ECC") is included in the EEPROM device recently used, thereby achieving the improvement in its reliability and yield. The modified EEPROM having the built-in ECC circuit is disclosed, for example, in Digest of Technical Papers, pages 83 and 84, August 1988, SYMPOSIUM ON VLSI CIRCUITS. When a bit failure occurs during the use of the device, the user generally makes a correction by using the ECC operational. However, such an ECC operation can lead to a drop in the operation performance of the EEPROM, according to a data access time, current consumption, etc. Therefore, a manufacturer needs to measure, by a chip test, the data access time or the current consumption caused by using the ECC device according to the bit error, upon completion of manufacture of the EEPROM device. To easily achieve such measurement, there is required a device that is capable of generating an error bit in a desired bit position. However, in a known EEPROM device having therein a built-in ECC circuit, it is very difficult to completely measure the effect of ECC operation in the EEPROM, because of having no error-bit generating circuit therein.